Modern electronic devices such as notebook computers comprise a variety of memories to store information. Memory circuits include two major categories. One is volatile memories; the other is non-volatile memories. Volatile memories include random access memory (RAM), which can be further divided into two sub-categories, static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they will lose the information they store when they are not powered. On the other hand, non-volatile memories can keep data stored on them without power. Non-volatile memories include a variety of sub-categories, such as read-only-memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory.
SRAM systems, comprising SRAM cells, have the advantageous feature of holding data without a need for refreshing. A SRAM cell may have various numbers of transistors, such as eight transistors (8T) or six transistors (6T). The transistors in a SRAM cell may be metal-oxide-semiconductor field-effect transistors (MOSFET). The MOSFET transistor is a device made of semiconductor materials with four terminals—source, gate, drain, and body (substrate). The SRAM industry has experienced rapid growth due to continuous improvements in the integration density and repeated reductions in minimum feature size. However, the smaller feature size may lead to more leakage current for MOSFET transistors. As the demand for even smaller electronic devices has grown recently, there has grown a need for reducing leakage current of SRAM cells and SRAM systems.
Fin field-effect transistors (FinFET) have smaller device sizes and increased channel widths. Recent advances in FinFET transistor technology have made advanced SRAM cells using FinFET transistors possible. In contrast to the planar MOS transistor, which has a channel formed at the surface of a semiconductor substrate, a FinFET transistor has a three dimensional channel region. The active region of the FinFET transistor, like a fin, is rectangular in shape from a cross section view. The three-dimensional shape of the FinFET transistor channel region allows for an increased gate width without increased silicon area even as the overall scale of the devices is reduced with semiconductor process scaling. To maximize the channel width of a FinFET transistor, the FinFET transistor may include multiple fins, with the ends of the fins connected to a same source and a same drain.
Each bit in an SRAM system is stored on a SRAM cell. SRAM cells are typically arranged as an array having rows and columns. Each row of the SRAM cells is connected to a word line, which determines whether the current SRAM cell is selected or not. Each column of the SRAM cells is connected to a bit line (or a pair of complementary bit lines), which is used for writing a bit into, or reading a bit from, the SRAM cell. A SRAM cell has two stable states which are used to denote 0 and 1, controlled by a word line and bit lines. Although it is not strictly necessary to have two bit lines, both the signal and its complement are typically provided in order to improve noise margins. A SRAM cell may have three different states, sleep where the circuit is idle, reading (R) when the data has been requested, and writing (W) when updating the contents.
In the deep sub-micron technology, embedded SRAM (particularly 8T SRAM) systems become very popular storage units for high speed communication, image processing, and system on chip (SOC) products. SRAM systems need to have high bandwidth, low loading, high speed, and reduced current leakage for the small feature size and deep sub-micron technology.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.